3D Integrated Circuit and Methods of Forming the Same

ABSTRACT

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

This application is a continuation of U.S. patent application Ser. No.16/149,972, filed Oct. 2, 2018, and entitled “3D Circuit and Methods ofForming the Same,” which is a continuation of U.S. patent applicationSer. No. 15/018,422, filed Feb. 8, 2016, and entitled “3D Circuit andMethods of Forming the Same,” now U.S. Pat. No. 10,090,196 issued onOct. 2, 2018, which is a divisional of U.S. patent application Ser. No.14/056,345, filed Oct. 17, 2013, and entitled “3D Integrated Circuit andMethods of Forming the Same,” now U.S. Pat. No. 9,257,399 issued Feb. 9,2016, which applications are incorporated herein by reference.

BACKGROUND

In wafer-to-wafer bonding technology, various methods have beendeveloped to bond two package components (such as wafers) together. Theavailable bonding methods include fusion bonding, eutectic bonding,direct metal bonding, hybrid bonding, and the like. In the fusionbonding, an oxide surface of a wafer is bonded to an oxide surface or asilicon surface of another wafer. In the eutectic bonding, two eutecticmaterials are placed together, and are applied with a specific pressureand temperature. In various conditions, the eutectic materials aremelted. When the melted eutectic materials are solidified, the wafersare bonded together. In the direct metal-to-metal bonding, two metalpads are pressed against each other at an elevated temperature, and theinter-diffusion of the metal pads causes the bonding of the metal pads.In the hybrid bonding, the metal pads of two wafers are bonded to eachother through direct metal-to-metal bonding, and an oxide surface of oneof the two wafers is bonded to an oxide surface or a silicon surface ofthe other wafer.

The previously developed bonding methods have their disadvantages. Forexample, regarding the fusion bonding, extra electrical connections areneeded to interconnect he bonded wafers. Accuracy of the eutecticbonding is low, and there may be metal-squeeze due to the melting of thebonding metals. Throughput of the direct metal-to-metal bonding is alsolow. In the hybrid bonding, the metal pads have higher Coefficients ofThermal Expansion (CTEs) than the dielectric layers at the surfaces ofthe bonded wafers. This results in problems in bonding the dielectriclayers. For example, the bonds between the metal pads may delaminate ifthe expanded volume of the metal pads is smaller than the dishing volumeof the metal pads. Conversely, if the expanded volume of the metal padsis significantly greater than the dishing volume, the bonds between thedielectric layers may delaminate.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantagesthereof, reference is now made to the following descriptions taken inconjunction with the accompanying drawings, in which:

FIGS. 1 through 5 are cross-sectional views of intermediate stages inthe formation of a first package component in accordance with someexemplary embodiments;

FIGS. 6 through 9 are cross-sectional views of intermediate stages inthe formation of the first package component in accordance withalternative embodiments;

FIG. 10 illustrates a cross-sectional view of a second package componentin accordance with alternative embodiments; and

FIG. 11 illustrates the cross-sectional view of the bonding of twopackage components in accordance with some exemplary embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of various embodiments of the disclosure arediscussed in detail below. It should be appreciated, however, that theembodiments provide many applicable concepts that can be embodied in awide variety of specific contexts. The specific embodiments discussedare illustrative, and do not limit the scope of the disclosure.

A package including hybrid bonding and methods of forming the same areprovided in accordance with various exemplary embodiments. Intermediatestages of forming the package are illustrated. Variations of theembodiments are discussed. Throughout the various views and illustrativeembodiments, like reference numbers are used to designate like elements.

FIGS. 1 through 5 illustrate cross-sectional views of intermediatestages in the formation of a package component in accordance with someembodiments. Referring to FIG. 1, package component 100 is illustrated.Package component 100 may comprise a device wafer, a packaged wafer, aninterposer wafer, or the like. In the embodiments package component 100comprises a device wafer, package component 100 includes semiconductorsubstrate 102, which may be, for example, a silicon substrate. Othersemiconductor substrates such as silicon carbon substrates, silicongermanium substrates, and III-V compound semiconductor substrates arealso usable. Active devices 104 may be formed on a surface of substrate102, and may include, for example, transistors. Metal lines and vias 106are formed in dielectric layers 108, which may include Inter-LayerDielectric (ILD), Inter-Metal Dielectric (IMD) layers, passivationlayers, and the like. The ILD layer and the IMD layers may be low-kdielectric layers in some embodiments, which have dielectric constants(k values) smaller than a pre-determined value, such as smaller thanabout 3.5, smaller than about 3.0, smaller than about 2.5, etc.Dielectric layers 108 may include non-low-k dielectric materials havingdielectric constants (k values) equal to or greater than 3.8. Metaltraces 106 (which include metal lines and vias) may include copper,aluminum, nickel, tungsten, or alloys thereof. Metal lines and vias 106interconnect active devices 104, and electrically connect active devices104 to the overlying metal features 112.

In alternative embodiments, package component 100 is an interposerwafer, which is free from active devices therein. Package component 100may, or may not, include passive devices (not shown) such as resistors,capacitors, inductors, transformers, and the like in accordance withsome embodiments.

In yet alternative embodiments, package component 100 is a packagesubstrate. In some embodiments, package component 100 is a laminatepackage substrate, wherein conductive traces 106 are embedded inlaminate dielectric layers 108 as schematically illustrated. Inalternative embodiments, package components 100 are built-up packagesubstrates, which comprise cores (not shown), and conductive traces(represented by traces 106) built on opposite sides of the cores. Thecore of a built-up package substrate includes a fiber layer (not shown)and metallic features (not shown) penetrating through the fiber layer,with the conductive traces interconnected through the metallic features.The conductive traces 106 are interconnected through conductive featuresin the cores.

In various embodiments wherein package component 100 is a device wafer,an interposer wafer, a package substrate, or the like, dielectric layer110 is formed, which may be a top IMD layer. In some embodiments,dielectric layer 110 is a low-k dielectric layer having k value lowerthan about 3.0, lower than about 2.5, or lower than about 2.0. Inalternative embodiments, dielectric layer 110 comprises silicon oxide,silicon oxynitride, silicon nitride, or the like. Metal features 112 areformed in dielectric layer 110, and may be electrically coupled toactive devices 104 through metal lines and vias 106. Metal features 112may be metal lines or metal pads. Metal features 112 may also be formedof copper, aluminum, nickel, tungsten, alloys of the above-mentionedmetals, or other appropriate materials. The top surface of dielectriclayer 110 and the top surfaces of metal features 112 may besubstantially level with each other. In the embodiments wherein packagecomponent 100 is a device wafer, dielectric layer 110 and metal features112 may be on the front side (the side with active devices 104) or thebackside (the side underlying substrate 102) of substrate 102. Forexample, FIG. 1 illustrates that dielectric layer 110 and metal features112 are on the front side of substrate 102.

Each or some of metal lines and vias 106 and metal features 112 mayinclude a copper-containing region (not shown) and a conductive barrierlayer separating the copper-containing region from the respectivedielectric. The conductive barrier layer may include titanium, titaniumnitride, tantalum, tantalum nitride, or the like.

Referring to FIG. 2, a plurality of layers is formed. In someembodiments, the plurality of layers includes etch stop layer 114,non-porous dielectric layer 116 over etch stop layer 114, porousdielectric layer 118 over non-porous dielectric layer 116, anddielectric barrier layer 120 over porous dielectric layer 118. Theoverlying ones of the plurality of layers may be in physical contactwith the respective underlying layers. In some embodiments, etch stoplayer 114 comprises silicon carbide, silicon nitride, siliconoxynitride, or other dielectric materials. Non-porous dielectric layer116 may also be a non-low-k dielectric layer having a k value equal toor higher than about 3.8. Furthermore, the porosity of non-porousdielectric layer 116 may be lower than about 5 percent. When theporosity is lower than about 5 percent, non-porous dielectric layer 116does not have the function of releasing stress generated due to thesubsequent bonding of package components 100 and 200 (FIG. 11). In someexemplary embodiments, non-porous dielectric layer 116 is formed ofUn-doped Silicate Glass (USG), silicon oxide, or the like. The formationmethods of non-porous dielectric layer 116 may include a Chemical VaporDeposition (CVD) method such as High-Density Plasma CVD (HDPCVD), PlasmaEnhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition(ALD), or the like.

Porous dielectric layer 118 may also be a low-k dielectric having a kvalue lower than 3.8, or lower than about 3.0. The low-k dielectricmaterials having k values lower than 3.8 are low-k dielectric materials.The k value of dielectric layer 118 may also be between about 2.5 and3.0. Furthermore, the porosity of porous dielectric layer 118 is higherthan the porosity of non-porous dielectric layer 116. For example, theporosity of porous dielectric layer 118 may be higher than about 5percent and about 40 percent. When the porosity of porous dielectriclayer 118 reaches about 5 percent, porous dielectric layer 118 starts tocause releasing the stress generated due to the subsequent bonding ofpackage components 100 and 200 (FIG. 11). When the porosity of porousdielectric layer 118 further increases, the stress is released better.The porosity of porous dielectric layer 118 is selected to be lower thanabout 40 percent since when the porosity of porous dielectric layer 118reaches about 40 percent, porous dielectric layer 118 may breakdown. Insome exemplary embodiments, porous dielectric layer 118 comprises acarbon-containing dielectric. The formation methods of non-porousdielectric layer 116 may include SiO₂, Phosphosilicate Glass (PSG),Fluorine-doped Silicate Glass (FSG, or the like.

Dielectric barrier layer 120 comprises a dielectric material, which maybe, for example, a silicon-based dielectric such as silicon nitride,silicon oxynitride, or the like. Dielectric barrier layer 120 has thefunction of bonding to another die/wafer through fusion bonding, and mayalso block copper from diffusing through.

Referring to FIG. 3, an etching step is performed through aphotolithography process, and hence openings 122 are formed indielectric layers 114, 116, 118, and 120. In the etching step, etch stoplayer 114 is used to stop the etching, and then etch stop layer 114 isfurther etched to expose the underlying metal features 112. Openings 122thus have sidewalls 124 that continuously extend from the top surface ofdielectric barrier layer 120 to the top surface of metal features 112.In accordance with some embodiments, sidewalls 124 are substantiallystraight sidewalls that are substantially perpendicular to top surface102A of substrate 102, although sidewalls 124 may also be tilted.

Next, conductive barrier layer 126 and metallic material 128 are filledinto openings 122, resulting in a structure shown in FIG. 4. In someembodiments, conductive barrier layer 126 comprises titanium, titaniumnitride, tantalum, tantalum nitride, combinations thereof, multi-layersthereof, or other materials. Metallic material 128 may be acopper-containing material including substantially pure copper or acopper alloy. Metallic material 128 may also include aluminum, nickel,or the like.

A Planarization such as a Chemical Mechanical Polish (CMP) is thenperformed. Dielectric barrier layer 120 may be used as a CMP stop layer.As a result, the top surface of the remaining metallic material 128 iscoplanar with the top surface of dielectric barrier layer 120. Theresulting structure is shown in FIG. 5. The remaining portions ofconductive barrier 126 and the respective overlying metallic material128 are in combination referred to as bond pad 130 hereinafter. Themetal pads 130 may include dishing in some embodiments. As shown in FIG.5, each of bond pads 130 has a substantially straight edge continuouslyextending from the top surface of the dielectric barrier layer 120 tometal feature 112.

FIGS. 6 through 9 illustrate the formation of bond pads 130 anddielectric barrier layer 120 in accordance with alternative embodiments.These embodiments are similar to the embodiments in FIGS. 1 through 5,except dielectric barrier layer 120 (FIG. 9) is formed after theformation of bond pads 130, and may be formed using an organic materialsuch as a siloxane-based polymer. Referring to FIG. 6, etch stop layer114, non-porous dielectric layer 116, and porous dielectric material 118are formed. Openings 122 are then formed in layers 114, 116, and 118, sothat the underlying metal features 112 are exposed. Next, referring toFIG. 7, conductive barrier layer 126 and metallic material 128 arefilled into openings 122. A CMP is then performed to remove excessportions of conductive barrier layer 126 and metallic material 128,forming bond pads 130, as shown in FIG. 8. The top surfaces of theresulting bond pads 130 are coplanar with the top surface of porousdielectric material 118, although dishing may sometimes occur to bondpads 130. In a subsequent step, as shown in FIG. 9, a blanket dielectricbarrier layer 120 is formed over bond pads 130 and porous dielectricmaterial 118. A photolithography process is then performed to remove theportions of blanket dielectric barrier layer 120, which removes portionscovering bond pads 130. The photolithography process may be performedusing photo resist 132 as an etching mask. After the patterning ofdielectric barrier layer 120, photo resist 132 is removed.

In some embodiments, dielectric barrier layer 120 comprises asiloxane-based polymer. For example, the siloxane-based polymer may bethe SINR™ provided by Shin-Etsu Chemical Co., LTD. Thickness T1 ofdielectric barrier layer 120 may be smaller than about 1 μm, so that inthe subsequent bonding process, the expanded metallic material 128 (whenheated, for example) may protrude out of the top surface of dielectricbarrier layer 120, and contact the metal pad in another wafer/die.

FIG. 10 illustrates package component 200 to be bonded to packagecomponent 100 in FIG. 5 or FIG. 9. Package component 200 may have astructure similar to what is described for package component 100 (FIGS.5 and 9), and the details are not repeated herein. The materials of thefeatures in package component 200 may be found referring to the likefeatures in package component 100 as described referring to FIGS. 1through 9. The features corresponding to the features in packagecomponent 100 have reference numerals starting with number “1.” whilethe features corresponding to the features in package component 200 havereference numerals starting with number “2.”

Package component 200 may also be selected from a device wafer, aninterposer wafer, a package substrate, and the like. In the illustratedFIG. 10, package component 200 includes substrate 202, active devices204, dielectric layers 208, metal lines and vias 206 in dielectriclayers 208. In alternative embodiments, package component 200 does notinclude active devices such as transistors, diodes, or the like.

In some embodiments, package component 200 may also include etch stoplayer 214, non-porous dielectric layer 216, porous dielectric layer 218,dielectric barrier layer 220, and bond pads 230. Bond pads 230 mayfurther include conductive barrier layer 226 and copper-containingmetallic material 228 over dielectric barrier layer 216.

In alternative embodiments, package component 200 may not include porousdielectric layer 218. Rather, conductive barrier layer 226 may be formeddirectly over and contacting non-porous dielectric layer 216, which maycomprise USG, silicon oxide, or the like. In these embodiments, thestress applied to the bonded bond pads 130/230 (FIG. 11) and dielectriclayers in the subsequent bonding process are absorbed by porousdielectric layer 118 in package component 100.

Next, as shown in FIG. 11, package components 100 and 200 arepre-bonded. In the pre-bonding, package components 100 and 200 are firstaligned, with bond pads 130 of package component 100 aligned to bondpads 230 of package component 200. After the alignment, packagecomponents 100 and 200 are pressed against each other. Duringpre-bonding, a pressing force may be applied to press package components100 and 200 against each other, in which the pressing force may be lowerthan about 5 Newton per die, for example. In the embodiments dielectricbarrier layers 120 and 220 are formed of inorganic materials, thepre-bonding may be performed at the room temperature (for example,between about 21° C. to about 25° C.), although higher or lowertemperatures may be used. The bonding time may be shorter than about 1minute, for example.

In the embodiments wherein dielectric barrier layers 120 and 220 areformed of organic materials such as SINR, pre-bonding may be performedat an elevated temperature in the range between about 140° C. and about160° C. The pre-bonding may last, for example, for a period of time inthe range between about 1 minute and about 5 minutes. Furthermore, afterthe pre-bonding, a curing process may be performed to drive solvents indielectric barrier layers 120 and 220 out of the respective packagecomponents 100 and 200. In some exemplary embodiments, the curing isperformed at a temperature in the range between about 170° C. and about190° C. The curing may last, for example, for a period of time in therange between about 60 minutes and about 120 minutes. In the embodimentswherein dielectric barrier layers 120 and 220 are formed of inorganicmaterials, the curing step may be skipped.

After the pre-bonding, dielectric barrier layers 120 and 220 are bondedto each other. The bonding strength, however, are improved in asubsequent annealing step, in some embodiments. The bonded packagecomponents 100 and 200 may be annealed at a temperature between about300° C. and about 400° C., for example. The annealing may be performedfor a period of time between about 1 hour and 2 hours. When temperaturerises, the hydroxide (OH) bonds (if any) in surface dielectric layers110 and 210 break to form strong Si—O—Si bonds, and hence packagecomponents 100 and 200 are bonded to each other through fusion bonds(and through Van Der Waals force). In addition, during the annealing,the metal, such as copper, in bond pads 130 and 230 inter-diffuse toeach other, so that metal-to-metal bonds are also formed. In variousembodiments, the resulting bonds between package components 100 and 200are called hybrid bonds, which include both the metal-to-metal bonds andSi—O—Si bonds and are different from the metal-to-metal bonds only orSi—O—Si bonds only. After the bonding, the bonded package components 100and 200 are sawed into a plurality of packages 300. Each of the packagesincludes die 100′ and die 200′, which are the separated portions ofpackage components 100 and 200, respectively.

In the bonding process, temperature is increased above room temperature(for example, about 21° C.), and bond pads 130 and 230 expand. TheCoefficient of Thermal Expansion (CTE) of bond pads 130 and 230 ishigher than that of dielectric materials such as 114/214, 116/216,118/218, and 120/210. Therefore, a stress may be applied to pulldielectric barrier layers 120 and 220 apart from each other. After theelevated temperature of the bonding process, package components 100 and200 are cooled. During the cooling stage of the bonding process, on theother hand, bond pads 130 and 230 shrink, which causes stresses to begenerated. The stresses are applied on the bond pads and dielectricmaterials. These stresses may cause the delamination of bond pads anddielectric layers. In various embodiments of the present disclosure, theporous dielectric layers have the function of absorbing the stress, andhence the delamination of metal pads and dielectric layers is reduced.

In the bonded structure as shown in FIG. 11, stresses occur in theregions that are close to the interface between package components 100and 200. The stresses have different values in different regions.Simulation results indicate that the highest stress is very likely tooccur where the interface of dielectric barrier layers 120 and 220 joinsthe inter-diffused bond pads 130 and 230. The stress may cause thedelamination of dielectric barrier layers 120 and 220, and/or thedelamination of bond pads 130 and 230 if no porous materials are used.In various embodiments, the stresses are simulated on the structureshown in FIG. 11. The results obtained from the simulation indicatedthat in a first group of samples adopting the structure of theembodiments, no dielectric delamination and metal pad delamination werefound. As a comparison, a second group of samples having similarstructures as the embodiments were also formed, wherein the second groupof samples uses USG to form both layers 116 and 118. The resultsindicated that the second group of samples has a dielectric delaminationpercentage of about 30 percent and about 80 percent, and a metal paddelamination percentage of about 10 percent and about 50 percent.

In accordance with some embodiments, an integrated circuit structureincludes a package component, which further includes a non-porousdielectric layer having a first porosity, and a porous dielectric layerover and contacting the non-porous dielectric layer, wherein the porousdielectric layer has a second porosity higher than the first porosity. Abond pad penetrates through the non-porous dielectric layer and theporous dielectric layer. A dielectric barrier layer is overlying, and incontact with, the porous dielectric layer. The bond pad is exposedthrough the dielectric barrier layer. The dielectric barrier layer has aplanar top surface. The bond pad has a planar top surface higher than abottom surface of the dielectric barrier layer.

In accordance with other embodiments, an integrated circuit structureincludes a first die and a second die. The first die includes a top IMDincluding a low-k dielectric material, a top metal feature in the topIMD, an etch stop layer overlying the top metal feature and the top IMD,a non-porous dielectric layer over and contacting the etch stop layer,and a porous dielectric layer over and contacting the porous dielectriclayer. The first die further includes a first dielectric barrier layerover the porous dielectric layer, and a first bond pad extends from atop surface of the first dielectric barrier layer to the top metalfeature. The second die includes a second bond pad bonded to the firstbond pad, and a second dielectric barrier layer bonded to the firstdielectric barrier layer.

In accordance with yet other embodiments, a method includes forming afirst die, which includes forming a non-porous dielectric layer over atop metal feature, forming a porous dielectric layer over and contactingthe porous dielectric layer, forming a first dielectric barrier layerover the porous dielectric layer, and etching the non-porous dielectriclayer and the porous dielectric layer to form an opening, wherein thetop metal feature is exposed through the opening. The formation of thefirst die further includes filling the opening with a metallic materialto form a first bond pad in the opening. The first die is then bonded toa second die, wherein the first bond pad is bonded to a second bond padin the second die, and wherein the first dielectric barrier layer isbonded to a second dielectric barrier layer in the second die.

Although various embodiments and their advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the embodiments as defined by the appended claims. Moreover,the scope of the present application is not intended to be limited tothe particular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure, processes, machines, manufacture,compositions of matter, means, methods, or steps, presently existing orlater to be developed, that perform substantially the same function orachieve substantially the same result as the corresponding embodimentsdescribed herein may be utilized according to the disclosure.Accordingly, the appended claims are intended to include within theirscope such processes, machines, manufacture, compositions of matter,means, methods, or steps. In addition, each claim constitutes a separateembodiment, and the combination of various claims and embodiments arewithin the scope of the disclosure.

What is claimed is:
 1. A semiconductor device comprising: a firstcontact extending away from a planar surface of a substrate, the firstcontact having straight sidewalls; a first dielectric layer surroundinga first portion of the first contact, the first dielectric layer beingseparated from the planar surface; a second dielectric layer surroundinga second portion of the first contact, wherein the second dielectriclayer has a larger porosity than the first dielectric layer and whereinthe first dielectric layer is located between the second dielectriclayer and the substrate; and a dielectric barrier layer surrounding athird portion of the first contact, the dielectric barrier layer sharinga planar surface with the first contact.
 2. The semiconductor device ofclaim 1, wherein the straight sidewalls are perpendicular to a majorsurface of the substrate.
 3. The semiconductor device of claim 1,wherein the straight sidewalls are tilted with respect to a majorsurface of the substrate.
 4. The semiconductor device of claim 1,wherein the first dielectric layer has a porosity of less than about 5%.5. The semiconductor device of claim 4, wherein the first dielectriclayer comprises un-doped silicate glass (USG).
 6. The semiconductordevice of claim 1, wherein the second dielectric layer has a porosity ofbetween about 5% and about 40%.
 7. The semiconductor device of claim 1,wherein the first contact comprises a conductive barrier layer, theconductive barrier layer comprising titanium, titanium nitride,tantalum, or tantalum nitride.
 8. A semiconductor device comprising: asubstrate; and a contact structure over the substrate, the contactstructure comprising: a first layer comprising a first conductivematerial; a second layer comprising the first conductive material and afirst dielectric material; a third layer comprising the first conductivematerial and a second dielectric material, the second dielectricmaterial having a larger porosity than the first dielectric material,and wherein the second layer is located between the first layer and thethird layer; and a fourth layer comprising the first conductive materialand a first barrier layer, wherein the first conductive material isplanar with the first barrier layer along a surface facing away from thesubstrate.
 9. The semiconductor device of claim 8, wherein the firstdielectric material has a porosity of less than about 5%.
 10. Thesemiconductor device of claim 9, wherein the second dielectric materialhas a porosity of greater than about 5% and less than about 40%.
 11. Thesemiconductor device of claim 8, wherein the first barrier layer isfusion bonded to a second barrier layer.
 12. The semiconductor device ofclaim 11, wherein the first conductive material is metal-to-metal bondedto a second conductive material.
 13. The semiconductor device of claim8, wherein the first dielectric material comprises un-doped silicateglass (USG).
 14. The semiconductor device of claim 8, wherein the firstbarrier layer comprises a siloxane-based polymer.
 15. A semiconductordevice comprising: a semiconductor substrate with an active devicelayer; a metallization layer overlying the semiconductor substrate; afirst layer overlying the metallization layer; a contact isolationstructure overlying the first layer, the contact isolation structurecomprising: a first dielectric layer in physical contact with the firstlayer; a second dielectric layer in physical contact with the firstdielectric layer, the second dielectric layer having a larger porositythan the first dielectric layer; a barrier layer in physical contactwith the second dielectric layer, wherein each of the first dielectriclayer, the second dielectric layer, and the barrier layer have a planarsurface facing away from the semiconductor substrate; and a conductivecontact extending through the contact isolation structure and the firstlayer to make physical contact with the metallization layer, theconductive contact having straight sidewalls.
 16. The semiconductordevice of claim 15, wherein the straight sidewalls are perpendicular tothe semiconductor substrate.
 17. The semiconductor device of claim 15,wherein the straight sidewalls are tilted with respect to thesemiconductor substrate.
 18. The semiconductor device of claim 15,wherein the barrier layer has a thickness of less than about 1 μm. 19.The semiconductor device of claim 15, wherein the barrier layercomprises silicon oxynitride.
 20. The semiconductor device of claim 15,wherein the second dielectric layer has a k value of between about 2.5and 3.0.